1. Field of the Disclosure
The disclosure is directed generally to digital signal processing (DSP), more particularly to a limit equalizer output based timing loop for an analog to digital converter (ADC) and to a method of use of an ADC that provides improved timing and/or timing recovery.
2. Related Art
In order to generate a timing signal and/or timing recovery signal, such as a read channel clock for a read channel of an optical storage device, a conventional phase detector (PD) uses the output of a filter arranged downstream of the ADC output, such as a finite impulse response (FIR) filter, as a basis for the generation of the timing signal. Such an arrangement produces inferior performance because the output of the filter, which is used to provide signal equalization to the output of the ADC, causes the timing signal to be compromised. In particular, the filter causes a phase shift in the timing and/or timing recovery signal. This is based, in part, on the fact that the filter is designed predominantly to be adaptive to the density variation of the optical storage device and to focus offsets or other errors of the device or media that require a change in the equalization and the like. Moreover, the filter is designed with a partial response target to improve the performance of an associated detector circuit such as a Viterbi circuit. Thus, these two design criteria drive the timing signal to have a change in phase as noted above. Accordingly, it is difficult to design a filter, such as a FIR filter, that is well constrained to meet multiple diverse demands.
Additionally, readback signals from an optical storage device, such as a CD, DVD, HD DVD or Blu-Ray disc, also suffers from manufacturing defects common with the stamping process in the manufacture thereof, or writing of recordable media. Such defects include, for example, variations in pit size and the like. These defects may result in high and low amplitudes that are not equal. The defects may also cause the transitions between land and pit to be shifted. In particular, non-linearity defects cause a deterioration of the performance of the timing loop in the optical storage devices.
To address these issues, the related U.S. patent application Ser. No. 11/775,757 discloses a timing loop based on an ADC output, in which the slicer output and asymmetry compensated output are provided as inputs to a phase detector for deriving an error signal for the timing loop. However, in the situation where there is severe inter-symbol interference (ISI), the ADC output may not cross zero for short mark/space transitions, which may cause excess timing jitter when an asymmetry compensated ADC output is used directly to drive the timing loop.
Accordingly, there is a need for an improved timing loop that does not suffer excess timing jitter when ISI occurs.